Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors

Abstract

The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA NS JLTs were investigated via numerical simulation. Compared to bulk neutral channels, a pronounced surface accumulation channel limited the overall electrical characteristics of GAA NS JLTs at narrow widths. Additionally, the variation in Vth of GAA NS JLTs was much smaller than that in tri-gate JLTs. Quantum mechanical effects in GAA NS JLTs with a very narrow width were also investigated.