The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay requirements exceeds the fastest speed of a specific adder, no matter how small the difference is. To expand the design space and manage delay /area tradeoffs, we propose new adder architecture and a design methodology. The proposed adder architecture, named heterogeneous adder, decomposes an adder into blocks (sub-adders) consisting of carry-propagate adders of different types and precision. The flexibility in selecting the characteristics of sub-adders is the basis in achieving adder designs with desirable characteristics. We consider the area optimization under delay constraints and the delay optimization under area constraints by determining the bit-width of sub-adders using Integer Linear Programming. We demonstrate the effectiveness of the proposed architecture and the design method on 128bit operands. © Springer-Verlag Berlin Heidelberg 2007.
CITATION STYLE
Lee, J. G., Lee, J. A., Lee, B. S., & Ercegovac, M. D. (2007). A design method for heterogeneous adders. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4523 LNCS, pp. 121–132). Springer Verlag. https://doi.org/10.1007/978-3-540-72685-2_12
Mendeley helps you to discover research relevant for your work.