SecHLS: Enabling Security Awareness in High-Level Synthesis

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Abstract

In their quest for further optimization, High-level synthesis (HLS) utilizes advanced automatic optimization algorithms to achieve lower implementation time/effort for even more complex designs. These optimization algorithms are for the HLS tools' backend stages, e.g., allocation, scheduling, and binding, and they are highly optimized for resources/latency constraints. However, current HLS tools' backend is unaware of designs' security assets, and their algorithms are incapable of handling security constraints. In this paper, we propose Secure-HLS (SecHLS), which aims to define underlying security constraints for HLS tools' backend stages and intermediate representations. In SecHLS, we improve a set of widely-used scheduling and binding algorithms by integrating the proposed security-related constraints into them. We evaluate the effectiveness of SecHLS in terms of power, performance, area (PPA), security, and complexity (execution time) on small and real-size benchmarks, showing how the proposed security constraints can be integrated into HLS while maintaining low PPA/complexity burdens.

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APA

Shi, S., Pundir, N., Kamali, H. M., Tehranipoor, M., & Farahmandi, F. (2023). SecHLS: Enabling Security Awareness in High-Level Synthesis. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 585–590). Institute of Electrical and Electronics Engineers Inc. https://doi.org/10.1145/3566097.3567926

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