Abstract
An unintended consequence of technology scaling has increased power consumption in a chip. Without specialized solutions, level of power consumption and rate of change of power consumption is even greater during test. Power delivery during test is somewhat limited by mechanical and electrical constraints. This chapter introduces the basic concepts related to power and energy and describes typical manufacturing test flow and associated constraints with power delivery. It also describes various types of power droop mechanisms, thermal issues, and how they interfere with the test process. Test economics issues, such as throughput and yield loss, are also discussed to further develop the low-power test problem statement. © 2010 Springer-Verlag US.
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CITATION STYLE
Kundu, S., & Sanyal, A. (2010). Power issues during test. In Power-Aware Testing and Test Strategies for Low Power Devices (pp. 31–63). Springer US. https://doi.org/10.1007/978-1-4419-0928-2_2
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