Spectroscopic Ellipsometry for Inline Process Control in the Semiconductor Industry

Abstract

Building high-performance silicon CMOS or III/V devices requires many structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed by a masked or blanket etch process. Whenever possible, the depo-sition and etch processes are verified by a thickness metrology step. Typically, a latest-generation CMOS process flow contains about 100 thickness measurements, at least during the development of the technology. The metrology method of choice in the semiconductor industry is spectroscopic ellipsometry, because it is fast, non-destructive, and capable of measuring product wafers in small areas (30-50 µm beam diameter) set aside in the scribe grid. This chapter will describe several typical applications of ellipsometry in CMOS and III/V device manufacturing and address capabilities and limitations and how future basic research on optical properties of materials can benefit the industry. 18.1 Introduction Building a high-performance complementary metal-oxide-semiconductor (CMOS) processor (see Fig. 18.1) with eleven layers of metals requires about 75 photolayers [9]. Many of these are dopant implant layers and therefore only require after develop inspection (ADI), overlay, and critical dimension (CD) metrology for optical lithography. However, there are about 40 structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed by a masked or blanket etch process (wet or dry). Whenever possible, the deposition and etch processes are verified by a thick