Abstract
This paper proposes two novel implementation methods for the RSA cryptographic scheme. (1) The most efficient RSA implementation known to the present authors. This implementation achieves 50 Kbps at about 25 Kgates for a 512-bit exponent e and a 512-bit modulus N. Thus the efficiency is 2.0 bps/gate. (2) A systolic architecture useful for high-speed and efficient and flexible chip implementation of the RSA scheme.
Cite
CITATION STYLE
Iwamura, K., Matsumoto, T., & Imai, H. (1993). High-speed implementation methods for RSA scheme. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 658 LNCS, pp. 221–238). Springer Verlag. https://doi.org/10.1007/3-540-47555-9_20
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