Design and implementation of low-power MIL-STD-1553B bus controller

Abstract

The demand in avionics field is increasing day to day and looking for high reliability and efficiency. To accomplish this MIL-STD-1553 has evolved. It has accepted as an international standard for military applications. Due its high reliability and flexibility, it can be widely used in military and space applications. In order to meet the real-world specifications, it is required to optimize the area, power, and to improve the performance of the data bus. This paper aims at designing low-power MIL-STD-1553B BC compatible to Data Device Corporation (DDC). The design has been done using Verilog HDL and simulated using Mentor Graphics tools. The power calculations have done in Design Compiler tool. The functionality of the proposed design is verified in Xilinx ISE 13.4 and the target device used is Spartan 3E FPGA.