A hardware implementation of evolvable embedded system for combinational logic circuits using virtex 6 FPGA

Abstract

The main aim of this paper was to develop an architectural model using the concept of evolvable embedded system for design automation of VLSI circuits. The architecture is modeled for any combinational circuits with 8 inputs and outputs. An evolvable hardware system is an integration of evolutionary algorithm with a reconfigurable chip. A virtual reconfigurable architecture IP core modeled in the FPGA functions as a substrate for the evolution of combinational circuits. A genetic algorithm program to optimize the design procedure is carried out inside the soft core MicroBlaze microprocessor to speed up the evaluation process. The soft processor core along with the reconfigurable architecture is embedded into a single FPGA chip. An experimental model for a 2-bit adder and multiplier was validated to demonstrate the evolution of combinational circuits by evolvable embedded system hardware. This experimental setup is carried out on Virtex 6 (XC6VLX240T-1FFG1156) ML605 Evaluation Kit FPGA using the Xilinx Platform Studio 14.6 tools.