Coarse-Grained Reconfigurable Architectures

Abstract

Current trends in technology scaling, coupled with the increasing compute demands with a limited power budget, has spurred research into specialized accelerator architectures. Coarse-Grained Reconfigurable Architectures (CGRAs) have been shown to achieve higher performance and energy efficiency compared to conventional instruction-based architectures by avoiding instruction overheads with reconfigurable data and control paths. CGRAs also avoid the hardware and programming overheads of fine-grained alternatives such as Field-Programmable Gate Arrays (FPGAs) by raising the hardware abstraction. Designing efficient CGRAs requires a careful calibration of the granularity of its elements and building automated compilation flow to map high-level programs to the reconfigurable elements. This chapter reviews the challenges and opportunities in the field of CGRAs.