Spidergon STNoC is a state-of-the-art, low-cost on-chip interconnect that plays a vital role in enabling multiprocessor system-on-chip by providing structure, performance, and modularity. This chapter outlines topological and routing characteristics of the packet-switched Spidergon STNoC, focusing on its low diameter, vertex-symmetric, point-to-point chordal ring topology, and its low-cost, efficient deterministic, shortest-path routing algorithm. It also describes interesting design tools and discusses new Spidergon extensions toward fault tolerant routing.
CITATION STYLE
Tatas, K., Siozios, K., Soudris, D., & Jantsch, A. (2014). The Spidergon STNoC. In Designing 2D and 3D Network-on-Chip Architectures (pp. 161–190). Springer New York. https://doi.org/10.1007/978-1-4614-4274-5_7
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