NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory

Abstract

Various new non-volatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque transfer memory (STT-RAM, or MRAM), phase change memory (PCRAM), and resistive memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density-optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this work, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies including STT-RAM, PCRAM, ReRAM, and legacy NAND flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.