Design of Digital PLL Using Optimized Phase Noise VCO

Abstract

This paper emphasizes the CMOS implementation of PLL in 130nm technology using Mentor Graphics tool Pyxis. Most of the PLL uses VCO which depends upon variation of supply voltage for high tuning range. Whenever supply voltage changes, the stability will be effected by producing large variations in the frequency output. Since this paper gives the design of current starved or integrator VCO with Schmitt trigger circuit for PLL architecture where instead of varying supply varying the control voltage. In this paper transient analysis, phase noise analysis and jitter analysis of PLL is introduced. This low jittery PLL is further applicable in frequency synthesis, clock recovery that is mainly applicable for wireless communication systems. The PLL gets locked by producing output frequency 1.318GHz with -130dBc/Hz at offset of 10MHz and with cycle to cycle jitter of 5.98ps along with period jitter RMS of 4.92ns. The phase margin is also improved which is 66.280.