Design for eliminating operation specific power signatures from digital logic

Abstract

Conventional digital logic operations have distinguishable power signatures. Side channel power analysis combined with classification algorithm can reveal unknown logic operations. Revealing the underlying operations is the main task in reverse engineering an application. In this paper, we propose an unconventional way of overcoming this vulnerability by using chaos based reconfigurable logic operations. The chaos gate used in this paper is built from a simple 3 transistor chaotic oscillator capable of generating aperiodic states starting from a suitably chosen initial condition. We propose a design methodology using chaos gate to implement different logic operations with very similar power profiles. Therefore, it becomes significantly harder to distinguish logical operations built with chaotic logic gates in contrast to the conventional static CMOS logic gates. In addition, we show a mixed implementation of bitwise logic operations using different proportions of chaos and conventional gates resulting in a significant reduction of total overhead.