Abstract
Deep packet inspection (DPI) is widely used in content-aware network applications to detect string features. It is of vital importance to improve the DPI performance due to the ever-increasing link speed. In this demo, we propose a novel DPI architecture with a hierarchy memory structure and parallel matching engines based on memory-centric FPGA. The implemented DPI prototype is able to provide up to 60Gbps full-text string matching throughput and fast rules update speed.
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CITATION STYLE
Su, J., Chen, S., Han, B., Xu, C., & Wang, X. (2016). A 60Gbps DPI prototype based on memory-centric FPGA. In SIGCOMM 2016 - Proceedings of the 2016 ACM Conference on Special Interest Group on Data Communication (pp. 627–628). Association for Computing Machinery, Inc. https://doi.org/10.1145/2934872.2959079
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