FPGA Architecture for Kriging Image Interpolation

Abstract

This paper proposes an ultrafast scalable embeddedimage compression scheme based on discrete cosine transform.It is designed for general network architecture that guaranteesmaximum end-to-end delay (EED), in particular the DistributedMultimedia Plays (DMP) architecture. DMP is designed to enablepeople to perform delay-sensitive real-time collaboration fromremote places via their own collaboration space (CS). It requiresmuch lower EED to achieve good synchronization than that inexisting teleconference systems. A DMP node can drop packetsfrom networked CSs intelligently to guarantee its local delay anddegrade visual quality gracefully. The transmitter classifies visualinformation in an input image into priority ranks. Included in thebitstream as side information, the ranks enable intelligent packetdropping. The receiver reconstructs the image from the remainingpackets. Four priority ranks for dropping are provided. Ourpromising results reveal that, with the proposed compressiontechnique, maximum EED can be guaranteed with gracefuldegradation of image quality. The given parallel designs for itshardware implementation in FPGA shows its technical feasibilityas a module in the DMP architecture.