Speed enhancement with soft computing hardware

Abstract

During the past few years JPL has been actively involved in soft computing research encompassing theory, architecture, and electronic hardware. There are a host of soft computing applications that require orders of magnitude enhancement in speed compared to present day simulations on digital machines. For real-time computing this is made possible by selecting suitable algorithms, designing compatible architectures and implementing them in parallel processing hardware. A compact low-power hardware design for insitu applications uses a SD-packaged artificial neural network (ANN) multichip module performing object classification and recognition with 1012 multiply-sum operations per second (ops). Additionally, development on evolvable hardware (EHW) implemented on reconfigurable electronic hardware has shown exciting high-speed evolution of various digital and analog circuits. We review our work to demonstrate real-time processing. © Springer-Verlag Berlin Heidelberg 2003.