A Feasibility Study on Ferroelectric Shadow SRAMs Based on Variability-Aware Design Optimization

Abstract

A feasibility study on Ferroelectric Shadow SRAMs (FE-SRAMs) was performed using circuit simulations. To take into account design constraints set by the cell transistor variability, a simple operation margin search algorithm was proposed and used, which requires only pass/fail information from multiple transient simulations. It was found that stable dynamic recall operations can be achieved by using small enough ferroelectric capacitors, and that non-volatile write energy of well below 10 fJ/bit can be expected, adding minimal area penalty and performance degradation to the base SRAM cell. Scalability to advanced technology nodes is also anticipated. The results show that the FE-SRAM would be an ideal non-volatile memory solution for ultra-low power applications, such as sensor networks powered by energy harvesting.