A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

Abstract

This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application trough the design of a fully synthesizable four-stage-gain low-power operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is 1.75 μ A with 0.41- μ A standard deviation. Good robustness against supply and temperature variations is also found.