Design Arithmetic Circuits Using Quaternary Logic

Abstract

Arithmetic circuits play a really important role in each all-purpose and application specific procedure circuits. Multiple Valued Logic (MVL) provides the key good thing about the next density per computer circuit space compared to ancient 2 valued binary logic. Quaternary (Four-valued) logic conjointly offers the good thing about simple interfacing to binary logic as a result of base four (=22) permits for the utilization of straight forward encoding/decoding circuits. The purposeful completeness is well-tried with a collection of basic quaternary cells. The library of cells supported the Supplementary Symmetrical Logic Circuit Structure (SUSLOC) square measure designed, simulated, and accustomed build many quaternary fixed-point arithmetic circuits like adders, multipliers. These SUSLOC circuit cells square measure valid mistreatment SPICE models and also the arithmetic architectures square measure valid mistreatment System Verilog models for purposeful correctness. Quaternary (radix-4) twin quantity secret writing principles square measure applied to optimize power and performance of adder circuits mistreatment common place cmos gate technologies.