Abstract
Breakout routing is a single-layer wire-routing problem in which each of a set of pins must be connected to one of a set of vias, but no matching is prespecified. We propose a network-flow approach to breakout routing in which the wiring grid is modeled by a more compact graph. Our graph is a factor of θ(κ2) smaller than the wiring grid, where κ is the ratio of via spacing to pin spacing, which improves both the space and run time efficiency of the flow computation. A flow in the compact graph can be transformed into a wire layout, and vice versa.
Cite
CITATION STYLE
Hershberger, J., & Suri, S. (1997). Efficient breakout routing in printed circuit boards. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 1272, pp. 462–471). Springer Verlag. https://doi.org/10.1007/3-540-63307-3_83
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