Reconfigurable hardware architecture for compact and efficient stochastic neuron

Abstract

In this paper, we propose reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. This is used to build a feed-forward artificial neural network. For this purpose, we use field-programmable gate arrays i.e. FPGAs. However, as the state-of-the-art FPGAs still lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement the computation performed by a neuron. The multiplication an addition of stochastic values is simply implemented by an ensemble of XNOR and AND gates respectively. © Springer-Verlag Berlin Heidelberg 2003.