Automatic mapping of algorithms onto multiple FPGA-SRAM modules

Abstract

This paper describes the processes that have been developed to allow the automatic mapping of technology independent algorithms onto a network of reconfigurable hardware modules. The VHDL language is used at the behavioural level of abstraction to describe the algorithm. Each reconfigurable hardware module comprises of a single FPGA and SRAM. A mesh configuration of these modules provides the resources for data manipulation and data storage required by the algorithm. By pre-processing the algorithm prior to synthesis, and then performing network partitioning on the synthesised netlist, a hardware implementation is realised on multiple modules. This approach means that an algorithm may be mapped onto a versatile hardware system which is not constrained by the limitations of the target technology.