A low-complexity peak cancellation scheme and its FPGA implementation for peak-to-average power ratio reduction

Abstract

The power amplifier (PA) is the most power-hungry component in a wireless base station transmitter, and reducing the peak-to-average power ratio (PAPR) of wireless signals is an important issue for its effective use. In this paper, we focus on a field-programmable gate array (FPGA) implementation of the peak cancellation (PC) technique, which is known as the simplest method for PAPR reduction. The design issue of effective peak-cancelling pulses under the constraint on the out-of-band emission is addressed. In order to reduce its hardware complexity, a novel approach for generating peak-cancelling pulses is also presented. The experimental results based on long-term evolution (LTE)/LTE-Advanced and multi-band Wideband Code Division Multiple Access (WCDMA) signals demonstrate the validity of the proposed scheme. It has been shown that the proposed PC scheme can achieve lower in-band distortion than the conventional PC with an acceptable loss in out-of-band performance. Our study also includes mapping the signal processing methods onto a Xilinx virtex-7 FPGA device running at 245.76 MHz and addresses the resource utilization and the hardware design in detail.