PARALLEL ARCHITECTURES FOR HIGH PERFORMANCE GRAPHICS SYSTEMS.

Abstract

A framework is proposed for categorising parallel display architectures, ranging from 'polygon serial' (one processor per pixel) to 'pixel serial' (one processor per polygon or object). A variety of proposed architectures is discussed in relation to this framework, including the Pixel-planes system of Fuchs et al, the 8 multiplied by 8 display of Sproull et al and the Zone Management Processor system of Grimsdale et al.