RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor

Abstract

Recent times low/variable precision floating point operations have found its significance in the areas of AI, ML and IoT which need a balanced criterion like low-power/energy, area, high-performance, variable dynamic range/precision depending on the applications. The options are IEEE 754-2008 half (HP)/single (SP)/double (DP) precision floating point (FP) or the new data-type, POSIT [20]. Moreover, instructions set enabled computations provide flexibility for the applications. This paper presents a design of IEEE 754-2008 [11] half precision floating point (HP-FP)instruction set extensions (ISE) for RISC-V ISA [1] and details the architectures of various functional units of the co-processor. The out-of-order execute, in-order commit/retire co-processor supports half-precision addition, subtraction, division, square root, multiplication, fused multiply and accumulate, sign injection and compare. The co-processor accepts three half precision data operands, rounding mode and the associated op-code fields for computation. Each floating point computation is tagged with an instruction token to enable out-of-order execution, in-order completion and commit. The proposed modular floating point co-processor enables integration with integer pipeline. The RISC-V instruction set enabled half-precision co-processor has been verified using Berkeley soft-float test suites, synthesized for ASIC and FPGA and implemented on FPGA. A performance of 236 MHz on Xilinx Virtex-6 xcvlx550t FPGA and 555 MHz on 65 nm had been achieved.