Design and Implementation of Low-Power Memory-Less Crosstalk Avoidance Codes Using Bit-Stuffing Algorithms

Abstract

The crosstalk problems of interconnects are one of the main problems in DSM of switching network high-speed buses. To avoid the problem of crosstalk, we provided the crosstalk avoidance codes (CACs) to avoid the crosstalk problem. In this chapter, we will traverse and then produce FTC that should not have opposed directions of transitions, any direction of n number of neighboring wires in the channel. In this, we proposed a new method called a low-power algorithm for sequential and parallel bit stuffing. The low-power algorithm is for sequential and parallel bit stuffing by just inserting inverters (NOT gate) by avoiding the opposite transitions in the channel. We show the results of both algorithms (serial and parallel) of bit-stuffing (bus encoding) simulations and bit-removing (bus decoding) simulations using Verilog HDLs and synthesis and implement in FPGA. Compared to sequential bit stuffing, algorithms are somewhat more rapidly fast than the bit stuffing. And also we are finding the coding rate of both algorithms. The algorithms achieved not only higher coding rates but also lower power. Finally, we can extend the bit stuffing encoding system for generating forbidden transition codes (FTC) that avoid the two transition patterns, “01→10” and “10→01”, on any four adjacent wires.