A model of pipelined mutual exclusion on cache - Coherent multiprocessors

Abstract

This paper proposes a model of pipelined mutual exclusion on cache - coherent multiprocessors that allows processors to concurrently access different memory locations of shared data in a pipelined manner. The model converts the effective unit of mutual exclusion from shared data to one memory location, by producing the total order of requests for each location while preserving the total order for shared data in the order for location. Two implementations of the model are evaluated. © Springer-Verlag 2003.