Hardware-focused performance comparison for the standard block ciphers AES, Camellia, and triple-DES

Abstract

This paper describes compact and high-speed hardware architectures for the 128-bit block ciphers AES and Camellia, and reports on their performances as implemented using ASIC libraries and an FPGA chip. A 3-key triple-DES implementation is included for comparison. Small S-Box hardware designs using composite field inverters are also described, and are contrasted with conventional S-Boxes generated from truth tables. In comparison with prior work, our architectures obtained the smallest gate counts and the highest throughputs for both of the ciphers. The smallest designs were 5.32 Kgates with a throughput of 235 Mbps for the AES, 6.26 Kgates with 204 Mbps for Camellia, and 5.74 Kgates with 170 Mbps for the triple-DES by using a 0.18-μm library. The highest throughputs of 3.46 Gbps with 36.9 Kgates, 2.15 Gbps with 29.8 Kgates, and 1.07 Gbps with 17.0 Kgates were obtained for the AES, Camellia, and triple-DBS respectively, using a 0.13-μm library. © Springer-Verlag Berlin Heidelberg 2003.