Propagation delay analysis for bundled multi-walled CNT in global VLSI interconnects

Abstract

Multi-walled carbon nanotube (MWCNT) bundle potentially provided attractive solution in current nanoscale VLSI interconnects. This research paper introduces an equivalent single conductor (ESC) model for bundled MWCNT that contains a number of MWCNTs with different number of shells. A driver-interconnectload (DIL) system employing CMOS driver is used to calculate the propagation delay. Using DIL system, propagation delay is compared for bundled CNT structures containing different number of MWCNTs. At global interconnect lengths, delay is significantly reduced for the bundled CNT containing more number of MWCNTs with lesser number of shells. It is observed that compared to the bundles containing lesser number of MWCNTs, the overall delay is improved by 9.89% for the bundle that has more number of MWCNTs.