A VHDL design methodology for FPGAs

Abstract

As synthesis becomes popular for generating FPGA designs, the design style has to be adapted to FPGAs for achieving optimal synthesis results. In this paper, we discuss a VHDL design methodology adapted to FPGA architectures. Implementation of storage elements, finite state machines, and the exploitation of features such as fast-carry logic and built-in RAM are discussed. Using the design style described in this paper, small changes in the VHDL code can lead to dramatic improvements (a factor of 4), while optimizing key parts to the specific FPGA technology can reduce resource usage by more than a factor of 50.