Abstract
We present a compact model to estimate quickly and accurately the leakage power in CMOS nanometer Integrated Circuits (ICs). The model has similar accuracy than SPICE and represents an important improvement with respect to previous works. It has been developed to be used for fast and accurate estimation and optimization of the standby power dissipated by large circuits. © Springer-Verlag Berlin Heidelberg 2005.
Cite
CITATION STYLE
Rosselló, J. L., Bota, S., & Segura, J. (2005). Compact static power model of complex CMOS gates. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 3728 LNCS, pp. 348–354). Springer Verlag. https://doi.org/10.1007/11556930_36
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