Design and implementation of an FPGA-based 1.452-Gbps non-pipelined AES architecture

Abstract

This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP). © Springer-Verlag Berlin Heidelberg 2006.