A dual-coding technique to reduce dynamic power dissipation in deep submicron (DSM) technology

Abstract

In a typical bus system, 10% of the power dissipation is static or leakage and 90% is dynamic power. Hence, dynamic power dissipation reduction is main objective of our current research work. In our current research work, power dissipation is reduced in deep submicron (DSM) technology. It has been found that 75% of dynamic power dissipation is due to coupling transitions, whereas only 25% is due to self-transitions. This paper develops a novel technique, dual coding algorithm, in which inter-wire capacitance considers sufficiently and reduces the average power dissipation due to coupling transition approximately up to 50–66.66% with an additional area penalty. The effectiveness of coding method has been tested using MATLAB. Transmission results are tested on bus of system on chip which is simulated on Xilinx and implemented on FPGA.