A hybrid memory hierarchy to improve cache reliability with non-volatile STT-RAM

Abstract

With the development of manufacturing technology, chips have more integration density. However, soft errors have become a sensitive concern in the design of computer systems. So, in this paper, it aims to find the potential vulnerable data and allocates it into a reliable Non-Volatile Memory (NVM) with the assistance of complier on a hybrid memory hierarchy with NVM. It has proposed a word level lifetime model of data cache for the purpose of vulnerability estimation and critical data protection. Then, it has abstracted the NVM-assisted cache vulnerability factor to evaluate the reliability of data cache and used to measure the impact on reliability of data cache. Since STT-RAM is used as NVM to build an on-chip SPM then the traditional compiletime data allocation method. The data has been better protected, and the reliability of the whole system can be improved naturally.