Task rearrangement on partially reconfigurable FPGAs with restricted buffer

Abstract

Partially reconfigurable FPGAs can be shared among multiple independent tasks. When partial reconfiguration is possible at runtime the FPGA controller can decide on-line were to place new tasks on the FPGA. Since on–line allocation suffers from fragmentation, tasks can end up waiting despite there being sufficient, albeit non–contiguous resources available to service them. Rearranging a subset of the tasks executing on the FPGA often allows the next pending task to be processed sooner. In this paper we study the problem of placing and rearranging tasks that are supplied by input streams which have constant data rates. When such tasks are rearranged, the arriving input data have to be buffered while the execution is suspended. We describe and evaluate a genetic algorithm for identifying and scheduling feasible rearrangements when moving tasks are reloaded from off–chip and buffer size is limited.