Compact hardware implementations are important for enabling security services on constrained devices like radio-frequency identification (RFID) tags or sensor nodes where chip area is highly limited. In this work we present compact hardware implementations of the block ciphers: mCrypton, NOEKEON, and SEA. Our implementations are significantly smaller in terms of chip area than the results available in related work. In case of NOEKEON, we even provide the first hardware-implementation results of this algorithm at all. Our implementations are designed as stand-alone hardware modules, contain an 8-bit interface for communication, and support encryption as well as decryption operation. We give results for different datapath widths and evaluate also the impact of using shift registers or latch-based memory instead of flip flops. The most-compact implementation of mCrypton requires 2 709 GEs when using a 130 nm CMOS process technology from Faraday. NOEKEON and SEA consume 2 880 and 2 562GEs, respectively. © Springer-Verlag 2012.
CITATION STYLE
Plos, T., Dobraunig, C., Hofinger, M., Oprisnik, A., Wiesmeier, C., & Wiesmeier, J. (2012). Compact hardware implementations of the block ciphers mCrypton, NOEKEON, and SEA. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 7668 LNCS, pp. 358–377). https://doi.org/10.1007/978-3-642-34931-7_21
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