In this chapter, we will look at modeling finite state machines (FSMs). An FSM is one of the most powerful circuits in a digital system because it can make decisions about the next output based on both the current and past inputs. Finite state machines are modeled using the constructs already covered in this book. In this chapter, we will look at the widely accepted three-process model for designing a FSM.
CITATION STYLE
LaMeres, B. J. (2019). Modeling Finite State Machines. In Quick Start Guide to Verilog (pp. 113–127). Springer International Publishing. https://doi.org/10.1007/978-3-030-10552-5_8
Mendeley helps you to discover research relevant for your work.