A 24-bit sigma-delta ADC with configurable chopping scheme

Abstract

This paper presents a low-power high-precision sigma-delta analog-to-digital converter (ADC) mainly used for DC measurement, especially in applications with high input impedance. A configurable chopping scheme is proposed to reduce the input-dependent residual offset caused by the clock feed-through. Furthermore, it also improves noise performance in the first integrator. The 1.17mm2 chip is fabricated in a standard 65nm CMOS process. Measurement results show that the ADC achieves 20-bit resolution, 10 ppm INL and a 0.6μV offset, while consuming 860μW from 3.3V supply.