SVtL: System verification through logic tool support for verifying sliced hierarchical statecharts

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Abstract

SVtL is the core of a slicing-based verification environment for UML statechart models. We present an overview of the SVtL software architecture. Special attention is paid to the slicing approach. Slicing reduces the complexity of the verification approach, based on removing pieces of the model that are not of interest during verification. In [18] a slicing algorithm has been proposed for statecharts, but it was not able to handle orthogonal regions efficiently. We optimize this algorithm by removing false dependencies, relying on the broadcasting mechanism between different parts of the statechart model. © Springer-Verlag Berlin Heidelberg 2007.

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APA

Van Langenhove, S., & Hoogewijs, A. (2007). SVtL: System verification through logic tool support for verifying sliced hierarchical statecharts. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 4409 LNCS, pp. 142–155). Springer Verlag. https://doi.org/10.1007/978-3-540-71998-4_9

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