System Level Exploration for the Integration of Optical Networks on Chip in 3D MPSoC Architectures

Abstract

Design trends for next-generation multi-processor systems on chip (MPSoC) point to the integration of a large number of processing elements onto a single chip, requiring high-performance interconnect structures for high-throughput communication. On-chip optical interconnect and 3D die stacking are currently con-sidered to be the two most promising paradigms in this design context. New architec-tures based on these paradigms are currently emerging and new system-level approaches are required for their ef fi cient design. We investigate design tradeoffs for 3D MPSoC integrating optical networks-on-chip (ONoC) and highlight current and short-term design trends. We also propose a system-level design space exploration fl ow that takes routing capabilities of optical interconnect into account. The resulting application-to-architecture mappings demonstrate the bene fi ts of the presented 3D MPSoC architectures and the ef fi ciency of our system-level exploration fl ow. Keywords Optical network-on-chip (ONoC) • Multi-processor systems on chip (MPSoC) • 3D die stacking • Design space exploration