IP generator tool for efficient hardware acceleration of self-organizing maps

Abstract

In this paper, authors present an IP generator for FPGA-based hardware acceleration of Kohonen’s Self-Organizing Maps (SOM). The IP generator is realized in MATLAB and offers the user the possibility to design an efficient FPGA hardware accelerator with several settings such as the number of features and the number of neurons. The optimization is achieved by applying some approximations to the original SOM algorithm, these modifications do not affect the functionality of the map. The generated IP cores can be used both for training and inference and the software can check the clustering performances.