Design and implementation of moving average calculations with hardware FPGA device

Abstract

The article examines the design and implementation of the “moving average” procedure in the structure of FPGAs. It demonstrates that its implementation in the form of a recursive filter and the use of the DSP48A1 digital signal processing unit, embedded in the Xilinx Spartan 6 FPGA series, guarantee minimal logical resources. An estimation of the speed and dynamic range of the device is provided.