Static patterns matching for high speed networks

Abstract

In response to the need of a large number of static pattern matching on high-speed network, this paper presents a FPGA-based hardware implementation of static pattern matching, which can process in parallel by using the matrix-and algorithm. This method can not only reduce the complexity of programming but also provide the basic of reconfigurable implementation. Experimental results show that the realization is able to reach the theoretical bandwidth multiplying clock frequency by input data width. © 2012 Springer-Verlag.