Efficient floating-point implementation of high-order (N)LMS adaptive filters in FPGA

Abstract

Adaptive filters are used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. This paper deals with floating-point-like implementation of LMS and NLMS algorithms using FPGA hardware. We present an optimized cores for both algorithms, built using logarithmic arithmetic which provides very low cost multiplication and division. The designs are Grafted to make efficient use of the pipelined logarithmic addition/subtraction units. The resulting cores can be clocked at more than 80 MHz on the one million gate Xilinx XC2V1000-4 FPGA performing 295 MFLOPS. They can be used to implement adaptive filters of orders 20 to 1022 with a sampling rate exceeding 70 kHz. © Springer-Verlag Berlin Heidelberg 2006.