Design, Implementation And Characterization Of Xor Phase Detector For Dpll In 45 Nm Cmos Technology

Abstract

In this paper the implementation of XOR phase detector in 45 nm submicron CMOS technology and it's CMOS design layout using Microwind 3.1 for Digital Phase Locked Loop in sub-nanometres CMOS Technology is presented. The input-output transfer characteristic of XOR phase detector is presented. The CMOS XOR phase detector produces error pulses on both rising and falling edges while the CMOS phase frequency detector will respond only to positive or negative transitions. XOR phase detector will try to lock on both rising as well as falling edge while the PFD (phase frequency detector) will lock on either rising edge or falling edge of reference signal and feedback signal.