Surface Potential Based Analytical Model for Hetero-Dielectric p-n-i-n Double-Gate Tunnel-FET

Abstract

In this work a piecewise Surface Potential based analytical model for a Hetero-Dielectric p-n-i-n Double Gate Tunnel FET has been developed which captures the device performance in all regions of operation i.e. Accumulation, Depletion and Inversion Region. Moreover, a comparative study among single High-k dielectric, single Low-k dielectric and Hetero-Dielectric TFET has been done. Here Vgs and Vds dependent explicit equations for surface potential have been derived which are subsequently been made to be channel length dependent. Furthermore, the electrostatic behavior of the device is studied in terms of Lateral Electric Field and Energy Band Diagram. The efficacy of the model has been validated through simulated results obtained using ATLAS device simulation software.