For mobile devices, this paper proposes a compact hardware (H/W) implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [4], Yamamoto et al. proposed the method of reducing temporary registers for the MISTY1 FO function (YYI-08), and implemented a very compact MISTY1H/W. This paper aims to design the smallest KASUMI H/W by the application of YYI-08 to KASUMI, which has a similarly structured MISTY1 FO function. We discussed the applicability and found the problems on register competition and logical equivalence in the simple application, so we propose the new YYI-08 improved for KASUMI and the compact H/W architecture. According to our logic synthesis on a 0.11-μm ASIC process, the gate size is 2.99 Kgates, which is the smallest as far as we know. © IFIP International Federation for Information Processing 2010.
CITATION STYLE
Yamamoto, D., Itoh, K., & Yajima, J. (2010). A very compact hardware implementation of the KASUMI block cipher. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 6033 LNCS, pp. 293–307). https://doi.org/10.1007/978-3-642-12368-9_23
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