High-Speed Steep-Slope GaInAs Impact Ionization MOSFETs (I-MOS) With SS = 1.25 mV/dec - Part II: Dynamic Switching and RF Performance

Abstract

Part I of this work described narrow bandgap GaInAs-based I-MOS devices with a minimum steep slope SS_{min} = 1.25 mV/dec maintained over 4 orders of magnitude in drain current, {I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} ratios >106 at 300 K (>109 at 15 K), and low operating voltages for a gate length of {L}_{G} = 100 nm. Part II focuses on the device time-domain switching capabilities and RF performance. Digital switching tests using a hybrid connected inverter reveal excellent capabilities for high clock rate operation. Simple circuit estimates indicate that the present 100 nm GaInAs I-MOS can operate with clock frequencies >10 GHz. The impact-ionization-induced hysteresis in the {I}_{D} - {V}_{GS} I-MOS characteristics does not play any role in dynamic switching of a digital inverter: the {n} -channel pull-down transistor turns on with a steep slope, but turns off classically with a higher threshold voltage which reduces the dynamic power dissipation per switching cycle. Factors impacting GaInAs I-MOS reliability are considered, and a physically motivated approach to enhance the reliability of III-V MOSFETs is proposed. We show that GaInAs-based I-MOS devices offer high analog cutoff frequencies and low-noise characteristics, suggesting applicability for digital and RF applications on a single technological platform. When benchmarked against other steep-slope technologies, GaInAs I-MOS shows the strongest steep slope, competitive {I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} ratios, and lowest operating voltage of any I-MOS transistor to date, without any back-gate/substrate bias.