A low-power Content-Addressable Memory (CAM) using pipelined search scheme

Abstract

A Content-Addressable Memory (CAM) is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this project, a low power content-addressable memory using pipelined hierarchical search scheme is implemented. The search operation is pipelined and the match-lines are broken to several segments. Whenever the stored words fail to match in their initial segments, the search operation is discontinued for subsequent segments, hence the power is saved. The proposed scheme has been implemented in a 64×64 bit ternary CMOS CAM. The schematics of both the pipelined and non-pipelined CAMs are designed. PSPICE power simulation is used to extract the power consumption of both memory designs. The simulation results demonstrate an effective overall power reduction in the pipelined CAM compared to non-pipelined architecture for the given example memory pattern. © Springer Science+Business Media B.V. 2010.