Power-aware multicore soc and NoC design

Abstract

This chapter examines system-level design of power-efficient systems-on-chip. It starts by examining the sources of power consumption, considering high-level techniques for power-efficient processing, storage and on-chip communication. It also discusses algorithmic- and architecture-driven software transformations and application embedding for power-efficient embedded software. Then, it provides a glimpse at research and development of computer-aided design tools for effective multicore SoC power estimation, analysis and optimization at different abstraction levels and especially system-level modeling, including efforts towards standardization of power formats to enable tool interoperability. Finally, it considers state-of-the-art runtime power management and optimization techniques, including dynamic voltage scaling (DVS), frequency scaling (DFS) and other NoC-based power saving mechanisms. This chapter concludes by briefly outlining future trends towards true system-level power-aware design, providing a large list of references for further study © 2011 Springer Science+Business Media, LLC.